View TDA7312_5816008.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TDA7312 digital controlled stereo audio processor input multiplexer: - 4 stereo inputs four selectable addresses two digital control outputs input and output for external equalizer or noise reduction sys- tem volume control in 1.25db steps treble and bass control two speaker attenuators: - independent speakers control in 1.25db steps - independent mute function all functions programmable via se- rial i 2 c bus description the TDA7312 is a volume, tone (bass and treble) balance (left/right) processor for quality audio appli- cations. control is accomplished by serial i 2 c bus microproc- essor interface. the ac signal setting is obtained by resistor networks and switches combined with operational amplifiers. thanks to the used bipolar/cmos tecnology, low distortion, low noise and low dc stepping are obtained. november 1999 ? sdip30 ordering number: TDA7312 pin connection (top view) 1/13
thermal data symbol description sdip30 unit r th j-pins thermal resistance junction-pins max 85 c/w quick reference data symbol parameter min. typ. max. unit v s supply voltage 6 9 10 v v cl max. input signal handling 2 vrms thd total harmonic distortion v = 1vrms f = 1khz 0.01 0.1 % s/n signal to noise ratio 106 db s c channel separation f = 1khz 103 db volume control 1.25db step -78.75 0 db bass and treble control 2db step -14 +14 db fader and balance control 1.25db step -38.75 0 db mute attenuation 100 db absolute maximum ratings symbol parameter value unit v s operating supply voltage 10.2 v t amb operating ambient temperature 0 to 70 c t stg storage temperature range -40 to 150 c test circuit TDA7312 2/13
block diagram TDA7312 3/13
electrical characteristics (refer to the test circuit t amb = 25c, v s = 9v, r l = 10k w , r g = 600 w , all controls flat (g = 0), f = 1khz unless otherwise specified) symbol parameter test condition min. typ. max. unit supply v s supply voltage 6 9 10 v i s supply current 8 11 ma svr ripple rejection 60 80 db input selectors r ii input resistance input 1, 2, 3 35 50 70 k w v cl clipping level 2 2.5 vrms s in input separation (2) 80 100 db r l output load resistance 2 k w e in input noise 2 m v volume control r iv input resistance 20 33 50 k w c range control range 70 75 80 db a vmin min. attenuation -1 0 1 db a vmax max. attenuation 70 75 80 db a step step resolution 0.5 1.25 1.75 db e a attenuation set error av = 0 to -20db av = -20 to -60db -1.25 -3 0 1.25 2 db db e t tracking error 2db v dc dc steps adjacent attenuation steps from 0db to av max 0 0.5 3 7.5 mv mv speaker attenuators c range control range 35 37.5 40 db s step step resolution 0.5 1.25 1.75 db e a attenuation set error 1.5 db a mute output mute attenuation 80 100 db v dc dc steps adjacent att. steps from 0 to mute 0 1 3 10 mv mv bass control (1) gb control range max. boost/cut +12 +14 +16 db b step step resolution 1 2 3 db r b internal feedback resistance 34 44 58 k w treble control (1) gt control range max. boost/cut +13 +14 +15 db t step step resolution 1 2 3 db digital outputs v cesat v out = low i c =1ma 0.2 0.3 v i leak i leakage v out = v s 10 m a TDA7312 4/13
electrical characteristics (continued) symbol parameter test condition min. typ. max. unit audio outputs v ocl clipping level d = 0.3% 2 2.5 vrms r l output load resistance 2 k w c l output load capacitance 10 nf r out output resistance 30 75 120 w v out dc voltage level 4.2 4.5 4.8 v general e no output noise bw = 20-20khz, flat output muted all gains = 0db 2.5 515 m v m v a curve all gains = 0db 3 m v s/n signal to noise ratio all gains = 0db; v o = 1vrms 106 db d distortion a v = 0, v in = 1vrms a v = -20db v in = 1vrms v in = 0.3vrms 0.01 0.09 0.04 0.1 0.3 % % % sc channel separation left/right 80 103 db total tracking error a v = 0 to -20db -20 to -60 db 0 0 1 2 db db bus inputs v il input low voltage 1 v v ih input high voltage 3 v i in input current -5 +5 m a v o output voltage sda acknowledge i o = 1.6ma 0.4 v address pin (internal 50k w pull down resistor). notes: sda, scl, dig out 1, dig out 2 pins are high impedance when v s = 0 (1) bass and treble response see attached diagram (fig.16). the center frequency and quality of the resonance behaviour can be choosen by the external circuitry. a standard first order bass response can be realized by a standard feedback network (2) the selected input is grounded thru the 2.2 m f capacitor. figure 2: signal to noise ratio vs. volume setting figure 1: noise vs. volume/gain settings TDA7312 5/13
figure 3: distortion & noise vs. frequency figure 4: distortion & noise vs. frequency figure 5: distortion vs. load resistance figure 7: input separation (l1 ? l2, l3, l4) vs. frequency figure 6: channel separation (l ? r) vs. frequency figure 8: supply voltage rejection vs. frequency TDA7312 6/13
figure 9: output clipping level vs. supply voltage figure 11: supply current vs. temperature figure 10: quiescent current vs. supply voltage figure 13: typical tone response (with the ext. components indicated in the test circuit) figure 12: bass resistance vs. temperature TDA7312 7/13
i 2 c bus interface data transmission from microprocessor to the TDA7312 and viceversa takes place thru the 2 wires i 2 c bus interface, consisting of the two lines sda and scl (pull-up resistors to positive supply voltage must be connected). data validity as shown in fig. 14, the data on the sda line must be stable during the high period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. start and stop conditions as shown in fig.15 a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high tran- sition of the sda line while scl is high. byte format every byte transferred on the sda line must con- tain 8 bits. each byte must be followed by an ac- knowledge bit. the msb is transferred first. acknowledge the master ( m p) puts a resistive high level on the sda line during the acknowledge clock pulse (see fig. 16). the peripheral (audioprocessor) that ac- knowledges has to pull-down (low) the sda line during the acknowledge clock pulse, so that the sda line is stable low during this clock pulse. the audioprocessor which has been addressed has to generate an acknowledge after the recep- tion of each byte, otherwise the sda line remains at the high level during the ninth clock pulse time. in this case the master transmitter can gen- erate the stop information in order to abort the transfer. transmission without acknowledge avoiding to detect the acknowledge of the audio- processor, the m p can use a simplier transmis- sion: simply it waits one clock without checking the slave acknowledging, and sends the new data. this approach of course is less protected from misworking and decreases the noise immunity. figure 14: data validity on the i 2 cbus figure 15: timing diagram of i 2 cbus figure 16: acknowledge on the i 2 cbus TDA7312 8/13
software specification interface protocol the interface protocol comprises: a start condition (s) a chip address byte, containing the TDA7312 address (the 8th bit of the byte must be 0). the TDA7312 must always acknowledge at the end of each transmitted byte. a sequence of data (n-bytes + acknowledge) a stop condition (p) TDA7312 address msb first byte lsb msb lsb msb lsb s10001 addr 2 addr 1 0 ack data ack data ack p data transferred (n-bytes + acknowledge) ack = acknowledge s = start p = stop software specification chip address 1 msb 0001addr 2 addr 1 0 lsb data bytes msb lsb function 0 1 1 0 0 0 0 0 0 1 1 1 b2 0 1 0 1 1 b1 b1 b1 d2 0 1 b0 b0 b0 d1 c3 c3 a2 a2 a2 s2 c2 c2 a1 a1 a1 s1 c1 c1 a0 a0 a0 s0 c0 c0 volume control speaker att l speaker att r audio switch bass control treble control ax = 1.25db steps; bx = 10db steps; cx = 2db steps; sx = input selector; d x = dig out pins addr2 addr1 chip address 0 0 88 hex 0 1 8a hex 1 0 8c hex 1 1 8e hex TDA7312 9/13
software specification (continued) data bytes (detailed description) volume msb lsb function 0 0 b2 b1 b0 a2 a1 a0 volume 1.25db steps 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 0 0 b2 b1 b0 a2 a1 a0 volume 10db steps 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 -10 -20 -30 -40 -50 -60 -70 for example a volume of -45db is given by: 0 0 1 0 0 1 0 0 speaker attenuators msb lsb function 1 1 0 0 0 1 b1 b1 b0 b0 a2 a2 a1 a1 a0 a0 speaker l speaker r 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 0 0 1 1 0 1 0 1 0 -10 -20 -30 11111 mute for example attenuation of 25db on speaker r is given by: 1 0 1 1 0 1 0 0 TDA7312 10/13
audio switch msb lsb function 0 1 0 d2 d1 s2 s1 s0 audio switch 1 1 1 1 0 0 1 1 0 1 0 1 stereo 1 stereo 2 stereo 3 stereo 4 0 1 0 1 dig. out 1 = 0 dig. out 1 = 1 dig. out 2 = 0 dig. out 2 = 1 bass and treble 0 0 1 1 1 1 0 1 c3 c3 c2 c2 c1 c1 c0 c0 bass treble 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 c3 = sign for example bass at -10db is obtained by the following 8 bit string: 0 1 1 0 0 0 1 0 status at power on reset volume = 78.75db treble = bass = +2db spkrs attenuators = mute input = stereo 1 dig. out 1 = dig. out 2 = 1 TDA7312 11/13
sdip30 (0.400") dim. mm inch min. typ. max. min. typ. max. a 5.08 0.20 a1 0.51 0.020 a2 3.05 3.81 4.57 0.12 0.15 0.18 b 0.36 0.46 0.56 0.014 0.018 0.022 b1 0.76 0.99 1.40 0.030 0.039 0.055 c 0.20 0.25 0.36 0.008 0.01 0.014 d 27.43 27.94 28.45 1.08 1.10 1.12 e 10.16 10.41 11.05 0.400 0.410 0.435 e1 8.38 8.64 9.40 0.330 0.340 0.370 e 1.778 0.070 e1 10.16 0.400 l 2.54 3.30 3.81 0.10 0.13 0.15 m0 (min.), 15 (max.) s 0.31 0.012 outline and mechanical data TDA7312 12/13
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the cons equences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics C printed in italy C all rights reserved purchase of i 2 c components of stmicroelectronics, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defined by ph ilips. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com TDA7312 13/13

▲Up To Search▲

Price & Availability of TDA7312

	To Download TDA7312 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .